W7500P Ethernet Chip IC MCU Integration TCPIP/M0/MAC with PHY | Инструменты

W7500P Ethernet Chip IC MCU Integration TCPIP/M0/MAC with PHY | Инструменты

Necessary conditions for Ethernet communication:

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1MCU 2 MAC 3 PHY 4 TCP/IP Stack

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Many say that the MCU with Ethernet interface, such as STM32F107, only has a MAC, but also expands the PHY, and then the protocol stack can be used. The W7500P solves one chip.

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W7500= TCP/IP Protocol Stack + M0+MAC Industrial Grade -40--80

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W7500P=TCP/IP protocol stack + M0+MAC +PHY quasi-industrial grade

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ARM Cortex-M0

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Maximum clock frequency 48MHz
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Full hardware TCP/IP core

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8 sockets
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Each socket has a maximum of 32KBSRAM
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MII (media independent interface)
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RAM

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Flash: 128KB
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SRAM: 16KB to 48KB (such as 32KB socket cache is used, the minimum available 16KB, if the socket cache is not used, the maximum available 48KB)
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ROM for Boot program storage: 6KB
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Clock, reset and supply management

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POR (power-on reset)
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Regulator: 3.3V to 1.5V
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8 to 24MHz external crystal oscillator
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Internal internal 8MHz RC oscillator
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Phase-locked loop for CPU clock
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ADC

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12bit, 8ch, 1Msps
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DMA

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6 DMA controller
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Peripherals: UARTs, SPIs
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GPIO

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53 I/Os (16 IO x 3ea, 5 IO x 1ea)
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Debugging mode

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Serial Debug (SWD)
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Timer/PWM

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Watchdog*1 (32-bit subtraction counter)
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Timer*4 (32-bit or 16-bit subtraction counter)
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PWM*8 (32 counter/timer with 6-bit programmable prescaler)
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Communication Interface

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3 UART (2 UARTs with FIFO and flow control, 1 single UART)
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2 SPI
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2 I2C (Master/Slave, Fast-mode (400 kbps))
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encryption

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1 RNG (random number generator): 32-bit random code
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Package : 64 TQFP (7×7 mm)
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Block diagram

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W7500P